Complementary metal oxide silicon (CMOS) integrated circuits are popular because of their low power consumption characteristics. An ideal CMOS circuit conducts a negligible amount of current when the CMOS circuit is in standby or a quiescent state. Therefore, when a CMOS circuit is not switching states, only a small amount of quiescent current should be conducted by the CMOS circuit. The quiescent current, commonly referred to as Iddq, is composed primarily of leakage current. Iddq is the IEEE symbol for the quiescent power supply current in metal oxide silicon (MOS) circuits. A faulty CMOS circuit may draw a significantly larger amount of current than a properly functioning CMOS circuit when in the quiescent state.
Typically, Iddq testing includes setting a threshold value of Iddq in which the integrated circuit being tested is failed if the Iddq current conducted by the integrated circuit exceeds the threshold value. The Iddq current is measured while inputs to the integrated circuit are driven high or low depending on pre-determined states of input test vectors. Iddq testing includes stepping through many different combinations of input test vectors to exercise the functionality within the integrated circuit. The test vectors can be generated by automatic test pattern generation (ATPG) software tools, or by integrated circuit designers.
FIG. 1 shows a standard CMOS gate 10 within an integrated circuit. FIG. 1 also shows the Iddq current conducted by the CMOS gate 10. FIG. 2 shows standard input (Vin) and output (Vout) waveforms of the CMOS gate 10. FIG. 2 also shows the Iddq current conducted by the CMOS gate 10 when there is a defect 21 and when there is not a defect 23.
An interconnect open is an open-circuit defect that occurs in the interconnect wiring of an integrated circuit. The interconnect open disconnects at least one logic gate from whatever is intended to drive the logic gate. The interconnect open results in a floating wire in the integrated circuit.
Continual increases in integrated circuit density and complexity requires integrated circuits to include more interconnections. The interconnections include vias which are particularly susceptible to breaking and resulting in open circuit interconnections. In many microprocessor designs, the number of vias exceeds the number of transistors. Therefore, interconnect wiring is a likely place for an open-circuit defect to occur.
Conventional Iddq testing does not target specific types of defects. Rather, conventional Iddq testing includes exercising the functionality of an integrated circuit hoping to trigger fabrication defects. The inputs to the integrated circuit are set high or low depending on test vectors which are generated to exercise the functionality of the gates within the integrated circuit. This methodology does detect many defects. However, this methodology is inadequate to detect all possible defects within CMOS circuits.
It is desirable to have a method of Iddq testing which provides for a greater likelihood of detection of open circuit defects of interconnection lines within integrated circuits. It is also desirable that the method be easily incorporated into presently existing Iddq integrated circuit defect detection testing